1. Technical Field
Embodiments of the disclosed invention are directed to a fan-out wafer level package for a semiconductor device, and in particular, to such a device that employs a redistribution layer manufactured on a sacrificial silicon wafer before attachment of semiconductor dice that are to be packaged.
2. Description of the Related Art
For manufacturers of semiconductor devices, there is a continuing desire to increase the density and reduce the size of the devices, so that more devices can be made on a single wafer of semiconductor material, and so that products that incorporate the devices can be made more compact. One response to this desire has been the development of chip scale packaging and wafer level packaging. These are packages that have a footprint that is very close to the actual area of the semiconductor die. They are generally direct surface mountable, using, e.g., ball grid arrays and flip chip configurations.
Another development is the reconfigured wafer, in which a semiconductor wafer is separated into individual dice, which are reformed into a reconfigured wafer, in which the dice are spaced some greater distance apart than on the original wafer, after which additional processing steps are performed on the devices. One benefit is that this provides increased area for each die for “back end” processes, such as the formation of contacts at a scale or pitch that is compatible with circuit board limitations, without sacrificing valuable real estate on the original wafer. Some packages of this type are sometimes referred to as a fan-out wafer level package, because the contact positions of the original die are “fanned out” to a larger foot print. A prior art method of manufacturing a fan-out package 100 is briefly outlined with reference to FIGS. 1-4.
As shown in FIGS. 1 and 2, dice 102 are individually positioned with their active faces 114 facing a laminate carrier strip 104, and held in position by an adhesive tape 106. A liquid molding compound is deposited over the dice 102 and subjected to a compression molding process during which the compound is cured into a hard layer 110. The molding compound is similar to the epoxy material commonly used to form conventional semiconductor packages.
After curing, the laminate carrier strip 104 and tape 106 are removed, leaving the layer 110 with a top surface 112 in which the original dice 102 are embedded with the active faces 114 of the dice exposed for additional connections, as shown in FIG. 3. A redistribution layer 116 is then formed on the layer 110, as shown in FIG. 4. A dielectric layer 118 is deposited over the top surface 112 and patterned to expose contact pads 120 of the original dice 102. A conductive layer is then deposited and patterned to form electrical traces 122. A second dielectric layer 124 is deposited and patterned, and a final conductive layer 126 is deposited and patterned to form redistributed contact pads 128. Solder bumps 130 are formed on the contact pads 128, and the layer 110 is cut at lines K, which define the kerf of the saw, to produce individual fan-out wafer level packages 100.